1) Field of the Invention
The present invention relates to a circuit which prevents electrostatic breakdown of MOS transistors constituting the semiconductor device (e.g. CMOS integrated circuit).
2) Description of the Related Art
In recent years, semiconductor integrated circuits are developed centering around the MOS transistor technique, and are increased in scale and speed by development of a micropatterning technique. In a present MOS integrated circuit, the following technique is dominated. The gate electrodes of a PMOS transistor and an NMOS transistor are connected to each other to be an input terminal, and both the drain electrodes are connected to each other to be an output terminal, so that a complementary MOS circuit (CMOS circuit) is constituted.
The gate electrode of MOS transistors constituting the CMOS circuit is formed with an electrode which is highly insulated and another electrode formed on the insulated electrode through a thin highly insulating film, and a capacitor is formed between the electrodes. Therefore, when the capacitor portion is electrically charged, a high voltage may be instantaneously applied to the outside through an electrode pad connected to the transistor. As a result, surge breakdown occurs in another transistor or the like, or the lifetime of the transistor is shortened.
In contrast to this, when a high voltage is instantaneously applied to the electrode pad connected to the transistor by a switching operation of an external mechanical switch or a semiconductor switch, the capacitor portion of the transistor is electrically charged to generate a high voltage, electrostatic breakdown may occur, or the lifetime of the transistor may be shortened.
Therefore, a countermeasure against such surge breakdown or electrostatic breakdown is an important factor in a semiconductor integrated circuit in order to maintain a high degree of reliability of products. On the other hand, due to shrinkage and micropatterning of a semiconductor integrated circuit in recent years, the countermeasure against the electrostatic breakdown cannot be easily carried out.
A countermeasure against electrostatic breakdown which is employed in a conventional semiconductor integrated circuit (semiconductor device) will be described below with reference to FIGS. 10 and 11. FIG. 10 is a circuit diagram which shows an example of a semiconductor device subjected to a conventional countermeasure against electrostatic breakdown. FIG. 11 is a sectional structural view which explains an operation of the semiconductor device shown in FIG. 10.
In FIG. 10, a method of a countermeasure against electrostatic breakdown for an NMOS transistor circuit is shown. In FIG. 10, an NMOS transistor 101 has a drain electrode D connected to an electrode pad 102, and a source electrode S and a back gate B connected to ground (GND).
A surge protection circuit 103 is arranged on a connection line between the drain electrode D and the electrode pad 102 of the NMOS transistor 101. The surge protection circuit 103 is constituted by a series circuit composed of two diodes D11 and D12. The diode D11 has a cathode connected to a power supply 104 and an anode connected to the connection line. The diode D12 has a cathode connected to the connection line and an anode connected to the ground (GND).
With this configuration, when a positive surge voltage is applied to the electrode pad 102, an electric current is conducted to the diode D11, and a surge current flows toward the power supply 104. For this reason, a current flowing to the drain electrode D of the NMOS transistor 101 becomes small. When a negative surge voltage is applied to the electrode pad 102, an electric current is conducted to the diode D12, and a surge current flows from the ground (GND) to the electrode pad 102. For this reason, a current flowing out of the drain electrode D of the NMOS transistor 101 becomes small. Therefore, the NMOS transistor 101 is not broken down, and surge breakdown is prevented.
However, as shown in FIG. 11, a P+ diffusion layer 111 on which the back gate B of the NMOS transistor 101 is formed is connected to the ground (GND). For this reason, when the input impedance of the NMOS transistor 101 on the basis of the electrode pad 102 is lower than that of the surge protection circuit 103, a surge current penetrates a junction surface between an N diffusion layer 112 in which the drain electrode D is formed and a P− well 113, passes through the P+ diffusion layer 111 and a P− substrate 114, and reaches the ground (GND) to cause electrostatic breakdown of the junction surface.
For this reason, in a conventional art, a transistor size is increased to increase a reverse withstand voltage between the N diffusion layer 112 in which the drain electrode D is formed and the P− well 113, so as to prevent the electrostatic breakdown. However, a reduction of a transistor size by reducing the chip size and micropatterning of processes according to the reduction makes the thickness of the N diffusion layer 112 in which the drain electrode D is formed further smaller. Therefore, it is difficult to obtain a sufficient surge withstand voltage.
The applicant of this application has developed a semiconductor device which can prevent electrostatic breakdown even though the semiconductor device is constituted by sufficiently micropatterned MOS transistors, and has applied the semiconductor in advance (undisclosed: Japanese Patent Application No. 2001-3501). The outline of the semiconductor device will be described below with reference to FIGS. 7A and 7B. FIGS. 7A and 7B are circuit diagrams which show the configuration of a semiconductor device, subjected to the countermeasure against electrostatic breakdown, which was applied by the applicant in advance.
FIGS. 7A and 7B show extracted MOS transistors constituting a CMOS integrated circuit. More specifically, FIG. 7A shows an example of a configuration in which a PMOS transistor is subjected to a countermeasure against electrostatic breakdown. FIG. 7B is an example of a configuration in which an NMOS transistor is subjected to a countermeasure against electrostatic breakdown.
In FIG. 7A, a PMOS transistor 21 has a source electrode S connected to a power supply 24 and a drain electrode D connected to an electrode pad 22. A surge protection circuit 23 is arranged for the PMOS transistor 21.
The surge protection circuit 23 is constituted by a series circuit composed of two diodes D1 and D2. The diode D1 has a cathode connected to the power supply 24. The diode D2 has an anode connected to the ground (GND). The anode of the diode D1 and the cathode of the diode D2 are commonly connected to the connection line between the drain electrode D and the electrode pad 22 of the PMOS transistor 21.
In this configuration, in order to make the input impedance of the PMOS transistor 21 on the basis of the electrode pad 22 higher than the input impedance of the surge protection circuit 23, a resistor 25 is arranged between the back gate B of the PMOS transistor 21 and the power supply 24.
Therefore, when a surge voltage is applied to the electrode pad 22, a surge current can be prevented by the resistor 25 from flowing through the back gate B of the PMOS transistor 21, and the electrostatic breakdown and short lifetime of the PMOS transistor 21 can be prevented.
In FIG. 7B, an NMOS transistor 31 has a drain electrode D connected to an electrode pad 32 and a source electrode S connected to the ground (GND). A surge protection circuit 33 is arranged for the NMOS transistor 31.
The surge protection circuit 33 is constituted by a series circuit composed of two diodes D3 and D4. The diode D3 has a cathode connected to a power supply 24. The diode D4 has an anode connected to the ground (GND). The anode of the diode D3 and the cathode of the diode D4 are commonly connected to the connection line between the drain electrode D of the NMOS transistor 31 and the electrode pad 32.
In this configuration, in order to make the input impedance of the NMOS transistor 31 on the basis of the electrode pad 32 higher than the input impedance of the surge protection circuit 33, a resistor 35 is arranged between the back gate B of the NMOS transistor 31 and the ground (GND).
Therefore, when a surge voltage is applied to the electrode pad 32, a surge current can be prevented by the resistor 35 from flowing through the back gate B of the NMOS transistor 31, and the electrostatic breakdown and short lifetime of the NMOS transistor 31 can be prevented.
However, when design is such that the back gate of the MOS transistor has a high impedance, in practical use in which the semiconductor device is operated by applying power, a potential easily changes due to disturbance, and a parasitic element is easily formed disadvantageously. This phenomenon will be described below with reference to FIGS. 8 and 9. FIG. 8 is a sectional structural view which explains the internal configuration and operation of a CMOS integrated circuit serving as a semiconductor device shown in FIG. 7. FIG. 9 is a circuit diagram which explains a latch-up phenomenon.
As shown in FIG. 8, a CMOS circuit 40 has a structure in which the PMOS transistor 21 and the NMOS transistor 31 are complementarily connected to each other. In FIG. 8, P+ diffusion layers 42 and 43 are formed on both the ends of the surface of a P− substrate 41, respectively. An N− well 46 and a P− well 47 are formed between the P+ diffusion layers 42 and 43 through an N+ floating layer 45.
The N− well 46 includes an N+ diffusion layer 48 having the back gate B, a P diffusion layer 49 in which a source electrode S is formed, and a P diffusion layer 50 in which a drain electrode D is formed. A gate electrode G is arranged between the P diffusion layer 49 and the P diffusion layer 50. These components constitute the PMOS transistor 21.
The P− well 47 includes an N diffusion layer 51 in which a drain electrode D is formed, an N diffusion layer 52 in which a source electrode is formed, and a P+ diffusion layer 53 having the back gate B. A gate electrode G is arranged between the N diffusion layer 51 and the N diffusion layer 52. These components constitute the NMOS transistor 31.
In the CMOS circuit 40, when a surge voltage is applied to the electrode pad 22, a surge current is just about flowing in the junction surface between the P diffusion layer 50 and the N− well 46 of the PMOS transistor 21. However, since the impedance of the back gate B of the PMOS transistor 21 is higher than that of the surge protection circuit 23 due to the presence of the resistor 25, the surge current flows into the surge protection circuit 23. In this manner, electrostatic breakdown of the junction surface can be prevented.
When the surge voltage is applied to the electrode pad 32, a surge current is just about flowing in the junction surface between the N diffusion layer 51 and the P− well 47 of the NMOS transistor 31. However, since the impedance of the back gate of the NMOS transistor 31 is higher than that of the surge protection circuit 33 due to the presence of the resistor 35, the surge current flows into the surge protection circuit 33. In this manner, electrostatic breakdown of the junction surface can be prevented.
However, when the back gates B of the PMOS transistor 21 and the NMOS transistor 31 have high impedance, a PNP transistor 61 and an NPN transistor 62 are easily formed as parasitic elements. The PNP transistor 61 uses the N− well layer 46 as a base, the P diffusion layer 49 of the N− well 46 as an emitter, and the P− well 47 as a collector. The NPN transistor 62 uses the P− well 47 as a base, the N diffusion layer 52 of the P− well 47 as an emitter, and the N− well 46 as a collector. These transistors are formed with the connection shown in FIG. 9.
As shown in FIG. 9, the base electrode of the PNP transistor 61 is connected to the power supply 24 through the resistor 25 together with the collector electrode of the NPN transistor 62, and the emitter electrode of the PNP transistor 61 is directly connected to the power supply 24. The base electrode of the NPN transistor 62 is connected to the ground (GND) through the resistor 35 together with the collector electrode of the PNP transistor 61, and the emitter electrode of the NPN transistor 62 is directly connected to the ground (GND).
More specifically, the PNP transistor 61 and the NPN transistor 62 constitute thyristors having a positive feedback. When the current gains of these transistors satisfy a certain condition and an electric current is conducted to one of the transistors, a large current flows between the power supply 24 and the ground (GND) through the junction surface, and a latch-up phenomenon which breaks down the element occurs. Therefore, the high impedance of the back gates B of the PMOS transistor 21 and the NMOS transistor 31 decrease a latch-up tolerance.